`timescale 1ns / 1ps
/******************************************************************************
*                                                                             *
* UTICA softcore v0.1                                                         *
*                                                                             *
* Copyright (c) 2012 Andrew D. Zonenberg                                      *
* All rights reserved.                                                        *
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/**
	@file ButtonArray.v
	@author Andrew D. Zonenberg
	@brief Array of four debounced push buttons
 */
module ButtonArray(
						clk,
						buttons,
						addr, wr, rd, din, dout, wmask, doutok);
	
	////////////////////////////////////////////////////////////////////////////////////////////////
	// IO declarations
	input wire clk;
	
	input wire[31:0] addr;
	input wire wr;
	input wire rd;
	input wire[31:0] din;
	output reg[7:0] dout = 0;
	input wire[3:0] wmask;
	output reg doutok = 0;
	
	input wire[3:0] buttons;
	
	////////////////////////////////////////////////////////////////////////////////////////////////
	// Generate a nice slow debouncing clock
	reg clk_slow_edge = 0;							//asserted for one clk cycle every 2^16 cycles (roughly 1 KHz at 80 MHz)
	reg[15:0] clkdiv = 0;
	always @(posedge clk) begin
		clkdiv <= clkdiv + 1;
		clk_slow_edge <= 0;
		if(clkdiv == 0)
			clk_slow_edge <= 1;
	end
	
	////////////////////////////////////////////////////////////////////////////////////////////////
	// Debounce the buttons
	
	wire[3:0] buttons_debounced;
	
	SwitchDebouncer btn0 (.clk(clk), .clken(clk_slow_edge), .din(buttons[0]), .dout(buttons_debounced[0]));
	SwitchDebouncer btn1 (.clk(clk), .clken(clk_slow_edge), .din(buttons[1]), .dout(buttons_debounced[1]));
	SwitchDebouncer btn2 (.clk(clk), .clken(clk_slow_edge), .din(buttons[2]), .dout(buttons_debounced[2]));
	SwitchDebouncer btn3 (.clk(clk), .clken(clk_slow_edge), .din(buttons[3]), .dout(buttons_debounced[3]));
	
	////////////////////////////////////////////////////////////////////////////////////////////////
	// Memory mapping logic (read only)
	// Note that MMU has already stripped off high-order bits of our address so we only care about the offset
	// (which must be zero)
	
	always @(posedge clk) begin
	
		dout <= 0;
		doutok <= 0;
	
		//Only allow reading from the base address, all other values return zero.
		//Always say output is OK or CPU will hang when reading unimplemented addresses
		//TODO: trigger segfault on unmapped reads?
		if(rd) begin
			if(addr == 0)
				dout <= {28'h0, buttons_debounced};			
			doutok <= 1;
		end
	
		//Writing is not implemented since it makes no sense for this device
		
	end

endmodule
